In DDR4, DDR5 and other serdes data communication implementations, a source synchronization input clock and data are received and transmitted through input/output pads. There can be multiple data bits and a single clock path. A clock tree is implemented to provide the input clock to various components. A large clock tree can result in a mismatch between data transmission and the clock path. Chip design needs to balance the clock and data skew to meet a skew specification.
The skew balance becomes challenging and meeting the skew specification can be difficult in a high data rate transmission due to the data bit and clock mismatch. The process variation of the chips can cause a delay mismatch between the data bits. The layout, IR drop, the clock tree and driver mismatch contribute to the mismatch between each of the data bits and the clock path. Through the data path, more skew accumulates due to the delay variation and mismatch.
Conventional approaches tune and trim the delay for each data bit through register programming. Tuning and trimming the delay for each bit can keep the skew within the skew specification margin. Tuning and trimming becomes more challenging as design moves to DDR5, which has a higher data transfer rate. Tuning and trimming causes extra effort for the bench and automated test equipment (ATE) validation.
It would be desirable to implement resynchronization of a clock associated with each data bit in a double data rate (DDR) memory system.